1. Field of Invention
The present invention relates to a method of manufacturing flash memory. More particularly, the present invention relates to a method of manufacturing the floating gate of a split-gate flash memory.
2. Description of Related Art
Nonvolatile memory is widely used in all kinds of electronic devices for storing structural data, program data and other repeatedly used data. Nonvolatile memory includes erasable programmable read-only memory (EPROM) and electrically erasable programmable ROM (EPROM), both having a flash memory structure.
In general, a flash memory unit has a floating gate and a control gate. The floating gate is made from polysilicon and is designed to hold electric charges. The control gate, on the other hand, is designed to control the storage and retrieval of data. The floating gate is under the control gate and is generally in a floating state not connected to any external circuit. The control gate is normally connected to a word line. Since data can be stored into, read from or removed from a flash memory a multiple of times, production growth is fast in the semiconductor industry.
FIG. 1 is a schematic cross-sectional view of a conventional flash memory unit. As shown in FIG. 1, a tunnel oxide layer 105, a floating gate 110, a polysilicon oxide layer 120, an oxide/nitride/oxide dielectric layer 125 and a control gate 130 are formed over a substrate 100. The substrate 100 also has a source terminal 135 and a drain terminal 140.
To erase data within the flash memory unit, the control gate 130 is connected to an external voltage source of about 14V. Utilizing the pointed tip 118 on the floating gate 110 to produce an intense electric field, electrons within the floating gate 110 are accelerated and injected into the control gate 130. Hence, the pointed tip structure 115 on the floating gate 110 is important for determining the efficiency of data removal.
FIGS. 2A through 2C are schematic cross-sectional views showing the progression of steps for producing a conventional split-gate flash memory.
As shown in FIG. 2A, a tunnel oxide layer 220, a doped polysilicon layer 225 and a silicon nitride layer 230 are formed in sequence over a substrate 200. Microlithographic and etching processes are carried out next to pattern the silicon nitride layer 230, thereby forming an opening 235.
A thermal oxidation is carried out, as shown in FIG. 2B. Hence, the doped polysilicon layer 225 that is exposed by the opening 235 is oxidized to form a polysilicon oxide layer 240.
The silicon nitride layer 230 is selectively removed using hot phosphoric acid. Using the polysilicon oxide layer 240 as an etching mask, the doped polysilicon layer 225 is etched to form a floating gate 225a, as shown in FIG. 2C.
Since the polysilicon oxide layer 240 is conventionally formed by a thermal oxidation, the uniformity of the layer, which is affected by doping concentration and size of the grains inside the layer, is difficult to control. Hence, the flash memory formed by the conventional method has an unstable and reliability issue.